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SPCP858A
High Integrated RF Mouse Controller

General Description
  • Introduction
    • SPCP858A, a new high integrated RF mouse controller solution developed by SunplusIT, is a designated design for the target fields of 2.4GHz mouse applications. The chip contains an 8-bit SUNPLUSIT CPU core with two timers, Timer0 and Timer1. Memory includes 8K bytes of OTPROM with 128 bytes of RAM (including stack buffers). In addition, it builds in a DC/DC converter and a LDO converter. The DC/DC converter can drive the maximum 90mA at 2.8v or 2.5v for off-chip applications and convert 2 batteries in series. The LDO converter can drive the maximum 5mA at 1.9v or 1.8v for external device. Furthermore, a 128-byte EEPROM is built in for users to change the vendor/product ID anytime and anywhere.
    • Typical Application
      2.4GHz wireless optical mouse
    • Terms
      Abbreviation Definition
      LVR Low Voltage Reset
      LVD Low Voltage Detection
      OTP One Time Programmable
      POR Power-On Reset
      SPI Serial Peripheral Interface


Features
  • CPU
    • Built-in 8-bit SUNPLUSIT CPU core with running frequency at up to 12MHz clock rate
  • Memory
    • 8KB OTPROM and 128B RAM
    • Built-in 128-byte EEPROM
    • Option bits located in the built-in EEPROM area are loaded before Power-On Reset
  • Power
    • Built-in a DC/DC converter, which can drive maximum 90mA at 2.8v or 2.5v through VDD_OUT1 for off-chip applications and convert 2 batteries in series.
    • Built-in a LDO converter, which can drive maximum 5mA at 1.9v or 1.8v through VDD_OUT2 for the external device
  • Clock
    • Built-in internal 6MHz oscillator and 18/24MHz PLL for outputting CLK to external mouse sensor
    • External 16MHz crystal
  • I/O
    • Up to 17 general purpose I/Os on 28-pin package
    • Programmable I/O direction with resistive pull-up/down control
    • One special design for clock output up to 24MHz
  • Memory
    • 16K bytes program (OTP) memory
    • 128 bytes EEPROM
    • 512 bytes user RAM
    • Three 8-byte FIFOs for USB endpoints EP0, EP1 and EP2
    • Two 64-byte FIFOs for USB endpoints EP3 and EP4
  • Timer
    • One 14-bit free-running timer with overflow interrupt and real time interrupt
    • One 8-bit re-loadable timer can be cascaded as a 16-bit timer
  • Input Capture
    • Two input-capture registers
    • Selectable edge trigger for capture input
    • Pulse or period measurement
  • SPI
    • Full-duplex or half-duplex synchronous serial communication
    • Supports master or slave mode
    • Selectable transfer rate from 46.9K to 3M bps
  • Reset Circuit
    • Low Voltage Detection (LVD)
    • Low Voltage Reset (LVR)
    • Watchdog Timer Reset
    • Illegal Address Reset
    • Software Reset
  • Power Saving Mode
    • STOP mode and WAIT (schedule wakeup) mode
    • One internal ring oscillator which supports schedule wakeup
  • Package
    • Supports 28 SSOP package and dice


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